1. Field of the Invention
The present invention relates to, for example, a mobile communication terminal apparatus, a variable gain amplifier circuit and a gain control circuit suitable for a mobile telephone compatible with W-CDMA systems, a PHS (Personal Handyphone System) telephone, or a PDA (Personal Digital (Data) Assistant) equipped with a wireless communication function.
2. Description of Related Art
A mobile communication terminal apparatus such as a typical cellular terminal etc. converts an RF received signal received by an antenna to a digital signal using an A/D converter, and provides to audio output and data output via digital signal processing after performing demodulation using a data demodulator. FIG. 9 is a block view showing a typical receive circuit of this kind of mobile communication terminal apparatus.
As shown in the drawings, at the receive circuit, an RF received signal received by an antenna 110 is converted to a baseband signal by an RF circuit 100 in accordance with an RF circuit control signal from a CPU 103. After this, after the baseband signal is converted to a digital signal by an A/D converter 101, and is supplied to a DSP (Digital Signal Processor) 104 via a data demodulator 102 as a digital signal. The signal provided to the DSP 104 is subjected to signal processing on the basis of data stored in memory means 105 such as ROM and RAM etc., and is outputted as audio etc. from output means such as a speaker 109 via a D/A converter 108. After being converted to a digital signal by the A/D converter 106, the audio signal input from a microphone 107 etc. is subjected to signal processing by the DSP and is then transmitted from the antenna 110 via a modulator and a transmission circuit (not shown).
Typically, a dynamic range of the received electric power level at the antenna 110 is 80 dB to 100 dB with a cellular system and an appropriate input level with respect to this is therefore desirable at the A/D converter 101. Namely, the current consumed by an A/D converter increases according to the size of the range to be converted. This means that if the received power level of the antenna is inputted as is to the A/D converter 101, it is necessary for the A/D converter 101 to have an extremely broad dynamic range. Large power consumption is therefore required in accompaniment with this broadening of the range, which effectively reduces the usefulness of a receiver.
A received signal with a level distribution over a broad range is therefore transmitted to the A/D converter 101 at an appropriate level using a so-called automatic gain control circuit (AGC circuit) at this common receiver. This brings about a design of superior effectiveness, as a result, where the dynamic range necessary at the A/D converter 101 is reduced and electrical power consumed at the receiver overall is reduced while only a small amount of electrical power is consumed at the AGC circuit.
Such AGC circuits include typically analog control-type circuits (VGA circuits: Voltage-controlled Gain Amplifiers) for varying voltage supplied as a control signal to control gain. In recent years, however, digital control-type circuits (PGA circuits: Programmable Gain Amplifiers) providing digital data as control signals so as to control gain in a discrete manner have become widely known.
A configuration for a direction conversion receiver (DCR) constituted by an RF circuit performing gain control using this kind of PGA is shown in FIG. 10. At a mixer 113 employing an Ich and a Qch, this DCR performs a direct conversion to a baseband signal using the same local frequency as the frequency received at the antenna 110. Gain is then controlled by a PGA group 114 arranged in a large number of stages.
This kind of DCR can easily be put into the form of a highly integrated IC making it possible to reduce the number of peripheral components and, as a result, particular note has been taken of this receiving method in recent years. With this DCR receiving method, gain switching of the receiver is executed for just a baseband frequency or for an FR frequency and a baseband frequency because in intermediate frequency (IF) is not used. In the example shown in FIG. 10, all gain switching is carried out using baseband signals. Namely, feedback control is performed to apply appropriate gain to baseband signals inputted from the mixer 113 using the four-stage PGA group 114 on the basis of a gain control signal provided by the CPU 103. As a result, it is possible to adjust the signal level outputted to the A/D converter 101.
An example of a typical PGA circuit is shown in FIG. 11. In order to control the PGA group 114, in FIG. 11, first, a so-called three-line data (clock, data, latch) signal is provided to a gain control circuit 115. The gain control circuit 115 then provides prescribed gain control information to the PGA circuits of each stage on the basis of this signal. As an advantage of this kind of PGA circuit is that the change in gain can be discrete, it is possible to use as a variable gain amplifier, for example, a feedback circuit of a negative feedback amplifier for an operational amplifier by switching over with a MOS switch.
It is possible to achieve a receiver at an extremely low price with this method because integration is straightforward using semiconductor circuits. As a result, in a large number of cases, it is possible to achieve a receiver with extremely desirable circuit characteristics with circuits consuming little power, having superior temperature characteristics, and having a broad dynamic range, etc. Further, each PGA is, for example, capable of changing the gain in 1 dB steps using a combination of a resistance value used in an operational amplifier and a switch. Further, arbitrary gain switching such as changing gain from, for example, a minimum gain to a maximum gain in one go using a control signal is also possible.
However, in a case where a PGA circuit is used in this variable gain amplifier, problems occur where an abrupt DC fluctuation is generated at an output terminal at the time of gain switching so that the PGA circuit enters a saturated state. Namely, when the PGA group 114 is controlled to give a large gain, own DC offset voltages of each stage of the PGA group 114 are also amplified. The output DC level therefore reaches a reference voltage level (VDD level) or a ground level (GND level) so that the PGA circuit enters a saturation state. Normal operation of the PGA circuit cannot be expected during this saturation state.
Because of this, a DC feedback circuit 116 as shown in FIG. 11 is provided at this PGA circuit. This DC feedback circuit 116 detects a direct current component (DC component) of an output signal, converts this to a negative phase, and performs addition processing (negative feedback) on an input signal at an adder 117. As a result of this, it is possible to offset the fluctuation component of the own DC offset voltage, the direct current value at the PGA circuit is stabilized, and the inconvenience of the PGA circuit entering the saturated state can be prevented.
In a case where, for example, the baseband circuit for the DCR receiver shown in FIG. 10 is used as a PGA circuit system as shown in FIG. 13, it is necessary to set a cut-off frequency of a low pass filter employed as the DC feedback circuit 116 to an extremely low value. Namely, it is necessary to ensure that dropping of a low-frequency component in a baseband amplifier is avoided in transmission characteristics for a signal from input to output. This is because dropping of the low frequency component in the transmission characteristics from an input signal to an output signal reach a level that is not permissible for a baseband amplifier in a case where the cut-off frequency is not set to an extremely low value.
However, the relationship between the level of the cut-off frequency of the DC feedback circuit 116 and the time constant of the DC feedback circuit 116 is a trade-off. This is to say that there is a problem where the time constant becomes larger as the cut-off frequency is set lower, so that the time until fluctuation in the DC voltage (DC voltage fluctuation) converges, that is, a DC voltage convergence time is delayed.
Namely, although the DC voltage largely fluctuates at this timing if the gain switching is carried out, in a case where the cut-off frequency is set low, a long period of time is required until the this DC voltage fluctuation converges to the original DC voltage. Further, in a case where a PGA gain is switched over from a comparatively low state to the vicinity of maximum gain upon the gain switching, or in a case where the gain is changed at a portion having a substantial influence on the output such as the first stage of a multistage PGA circuit etc., as shown in FIG. 12, the DC level is temporarily saturated, with DC convergence taking place gradually thereafter. As it is not possible to achieve an appropriate output for this DC voltage convergence time, the output signal symbol disappears, and depending on the case, it is possible that deterioration in a bit error rate (BER) may occur.
In order to shorten this DC voltage convergence time, a band switching signal is provided to the DC feedback circuit 116 at the timing of switching the gain as shown in FIG. 14, and control is exerted so as to switch over a cut-off frequency set to a low value up to this point temporarily to a high value cut-off frequency at the time of PGA gain switching. As a result, it is possible to make the DC voltage convergence time shorter as shown in FIG. 15 because it is possible to temporarily reduce the time constant of the DC feedback circuit 116.
A variable gain amplifier system disclosed in Japanese Patent Application Publication (KOKAI) No. 2001-36358 is well-known as a related art of the PGA circuit.
[Japanese Patent Document 1]
Japanese Patent Application Publication (KOKAI) No. 2001-36358.
However, in this method, even if it is possible to shorten the gain switching time, as shown in FIG. 15, instantaneous breaking of the level of the DC voltage fluctuation cannot be avoided, and it is difficult to completely avoid symbols disappearing altogether.
Further, a method of arranging a sample/hold circuit 118 at an output of the PGA group 114 as shown in FIG. 16 has been considered as a method for avoiding instantaneous DC voltage level fluctuation breaking. As shown in FIG. 17, this method is a method where instantaneous breaking of the DC level is suppressed by holding an output and having no output for a certain section.
In this method, even if it is possible to avoid the level breaking using an absence of output, while there is no output, a signal is not outputted, and it is not possible to prevent instantaneous disappearing of the symbols.
Therefore, even if it is possible to shorten the time constant of the feedback circuit or suppress instantaneous saturation by stabilizing the baseband using DC feedback, it is difficult to avoid instantaneous disappearing of a symbol.
An example implementation of a typically used PGA is shown in FIG. 18. In FIG. 18, the variable width of the PGA of the receiver is taken to be 100 dB, with this being covered as 25 dB per one stage using four stages of PGA. PGA1, PGA2 and PGA4 are only for coarse adjustment of fluctuation widths of 25 dB, and PGA3 is a fine adjustment PGA capable of changing in 1 dB widths.
The circuit of the fine adjustment PGA is complex compared to a coarse adjustment PGA. At this time, as shown in FIG. 18, the gain setting of each PGA is decided in accordance with the received signal level and a fixed received power (−20 dBm) can be provided at the A/D input level by performing control using digital data from outside so that this state is attained.
In FIG. 18, change in PGA1 of the first stage is switched from High to Low when the input level is −50 dBm. Changes in the first stage PGA1 are such that changes in the DC offset of PGA1 cause a great amount of amplification to occur in PGA2 onwards of the latter stage. This makes it very easy for DC fluctuation to occur and means that it is easy for the received symbol to disappear.
In a case where this kind of receiver is applied to, for example, mobile communication equipment such as a cellular phone and use in this environment is assumed, as shown in FIG. 19, the AGC performs a following operation at intervals in accompaniment with fluctuations in receive level due to so-called phasing. Because of this, PGA gain changes frequently. At this time, in the event that, for example, changes in gain occur frequently for the first stage (PGA1) of a multi-stage PGA so that changes in the received power level occur, as with A and B shown in FIG. 20, gain control state transitions occur frequently over a span of −50 dBm, and there is a possibility that the RF output of the receiver will be such that disappearance of symbols will be frequently repeated.